CMOS imagers are electronic camera or imaging chips implemented in CMOS (complementary metal/oxide/silicon) technology, the technology presently used to make a large fraction of analog electronic circuits, as well as virtually all digital electronics. The CMOS process uses n-channel and p-channel field-effect transistors, as well as typically diodes, resistors and capacitors.
A CMOS imager contains a light-sensitive area where an optical image is focused. The image is converted into an electrical signal at the light-sensitive area. The CMOS imager also typically includes surrounding support electronics that readout the electrical signal, producing an analog or digital video output signal.
The light sensitive area is divided into a two-dimensional array of picture elements, or pixels. Each pixel in the array converts the light that falls on that pixel over an integration time period into a single signal voltage that can be read out by the support electronics.
A schematic of a commonly used prior art photodiode pixel 10 is shown in FIG. 1. Of course, those skilled in the art recognize that a conventional imager may well have millions of pixels 10 in a given imager arranged in a two dimensional array of pixels 10 and that only a single pixel is represented by FIG. 1. The pixels 10 become sensitive to light impinging them during an integration time period when electrons are bled off a capacitor inherently associated with a photosensitive diode 12.
Immediately prior to the beginning of the integration time period the photo diode 12 is reset. When ΦReset goes high the reset transistor MReset is turned on draining away any accumulated charge in the photodiode 12 thereby reverse biasing the photodiode 12 with the voltage VDD. The reset transistor MReset is then turned off again when ΦReset goes low, isolating the photodiode 12 and initially leaving a voltage equal to VDD initially stored on the photodiode's internal capacitance. The integration time-period then begins and light incident on the pixel 10 generates an internal current in the photodiode 12, tending to discharge the capacitively stored voltage towards ground. The amount of discharge in a fixed amount of time (the integration time period) is proportional to the intensity of light incident on the pixel 10.
Then when ΦSelect goes high the pixel voltage is read out by turning on the select transistor MSelect. This allows the column current source to draw current through the source-follower transistor MSF, biasing it, while simultaneously allowing source-follower transistor MSF to drive the column bus or line 14. The source-follower transistor MSF acts like a single-transistor buffer amplifier and it causes the column bus 14 voltage to follow the photodiode 12 voltage (minus a fixed offset drop) allowing a signal representative of the photodiode voltage to be sampled on line 14.
A key figure of merit of a CMOS imager is its dynamic range, which is the range of signals which the imager can faithfully read out. It is usually expressed as a ratio of the largest readable signal to the smallest readable signal. The smallest readable signal is determined by the noise floor of the imager. This invention does not address the noise directly, so the noise floor need not be discussed further in any particular detail. However, noise reduction is discussed in passing in connection with a second embodiment which has certain noise reduction features and one purpose of the second embodiment is to demonstrate that the techniques disclosed herein are compatible with noise reduction techniques.
The largest readable signal is determined by the maximum signal swing that can be read out. The dynamic range is maximized by making the high end voltage as high as possible and the low end voltage as low as possible.
In a photodiode imager, the low end of this range is determined by the offset of the source-follower and its relation to other downstream electronics. Again the low end of the swing is not addressed by this disclosure and so again will not be discussed further.
The high end of the voltage swing is determined by how high one can set the photodiodes' initial reset voltage. This innovation is intended to increase the dynamic range by increasing the magnitude of this reset voltage.
The complementary nature of CMOS means that both n-channel and p-channel transistors are ordinarily available to the designer, and both types are used in some parts of the imager, such as in associated logic circuits. However, in most practical designs the pixel size is quite limited, usually being on the order of 10 μm for a typical imager. There is a minimum separation normally required between n-channel and p-channel transistors, and the amount of required separation normally means that one cannot mix transistor types within a pixel and keep the size of the imager small. Therefore all of the transistors in the pixel are typically of the same conductivity type, usually n-type (which is also called n-channel).
The three transistors shown in FIG. 1 are all therefore typically all of the same conductivity type and in modern circuits this means that they are preferably all n-channel transistors. The reset drive voltage is the positive supply voltage, VDD. A problem comes about because using an n-channel transistor (or generically a reset switch or transistor having the same conductivity type as the other transistors in the imager) as the reset switch limits the maximum diode reset voltage. In order for an n-channel transistor to be on, the gate voltage must be at least one threshold voltage (called VT) more positive than the source voltage of the transistor. Alternatively, one can say that the source must be more negative than the gate by at least VT. The same issue would arise for a p-channel imager, but in that case the polarities would be reverse.
While it is possible to overdrive the gate voltage of the reset transistor by certain means, this can damage the reset transistor, resulting in greatly reduced reliability. Therefore, in a standard configuration, the maximum gate voltage is the positive supply voltage VDD (usually either 5 volts or 3.3 volts, depending on the CMOS process used).
If the gate is held at VDD and source must be must be more negative than the gate by at least VT, then the maximum source voltage is VDD−VT for the transistor to remain on. If the source rises above this voltage then the transistor will tend to turn off. This effect limits the maximum reset voltage of the photodiode to VDD−VT. If the photodiode voltage is initially at ground and ΦReset goes high, then MReset will turn on and current will flow through it pulling the photodiode voltage up toward VDD. However, as the photodiode voltage approaches. VDD−VT, the gate-source voltage of the reset transistor MReset approaches the threshold and turns itself off, preventing its source voltage (which is the photodiode reset voltage on the cathode of photodiode 12) from increasing any further.
To be more precise, the transistor MReset does not abruptly shut off, but instead goes into subthreshold operation where the current decreases exponentially with increasing source voltage. This will allow the photodiode voltage to continue to increase slightly, but it does so logarithmically with time. For a practical reset time of tens of microseconds, the diode voltage can only climb a few millivolts above the cutoff VDD−VT. Even if the reset were continued for hours the diode voltage will only be raised by tens of millivolts above this limit.
For example, in a 3.3 V CMOS process, the threshold voltage VT is normally about one volt, but it is increased even further by the so-called body effect when its source is raised above ground. Let us therefore use a figure of 1.3 volts for the threshold voltage VT. The maximum photodiode reset voltage is then only 3.3 V−1.3 V=2.0 V.
The lowest value of the photodiode voltage that can be read out is limited by the other electronics, and may typically be about one volt. Therefore the maximum photodiode signal swing is perhaps only from 2 volts to 1 volt, or only a range of 1 volt of the 3.3 volt supply voltage VDD. The situation is only slightly better for 5V CMOS processes, and the trend in CMOS development is, if anything, towards lower supply voltages.
The presently disclosed technology is intended to circumvent the problem described above and allow the photodiode 12 to be reset to an initial reset voltage greater than VDD−VT, without having to resort to either overdriving the reset transistor gate or replacing the n-channel reset transistor with a p-channel one.